1. Field of the Invention
The present invention relates to a solid state imaging device. More particularly, the invention relates to enhancement in sensitivity of a solid state imaging device having a vertical overflow drain structure.
2. Description of the Prior Art
As the solid state imaging device, taking an example of an interline transfer type area image sensor, the prior art will be explained below.
FIG. 5 shows the overall construction of a common interline transfer type area image sensor. Optical information incident on a matrix-arrayed photoelectric conversion section 21 is converted into a signal charge by the photoelectric conversion section 21. Then the signal charge is transferred to a charge detecting section 24 connected to a horizontal transfer section 23 via a vertical transfer section 22 and the horizontal transfer section 23. The charge detecting section 24 is comprised of a floating diffusion layer (forming a cathode side portion of a diode D1) for converting the signal charge in voltage, and a two-stage source follower circuit connected thereto for impedance conversion. This source follower circuit comprises transistors T1, T2 serving as its driver transistors, and transistors T3, T4 serving as its load transistors, where a DC voltage V.sub.GG is applied to gates of the transistors T3, T4. Also, DC voltage is applied to a RD terminal and an OD terminal. After the diode D1 is reset by a reset pulse .phi.R applied to a gate of a reset transistor TR, the signal charge transferred from the horizontal transfer section 23 is further transferred to the floating diffusion layer via an output gate 25. Depending on the amount of this signal charge, voltage at point A changes, and the resulting voltage change is converted in impedance by the two-stage source follower circuit, and outputted from an output terminal OS.
Referring to FIG. 5, when a ray of intense light impinges on part of the matrix-arrayed photoelectric conversion section 21, there will occur the so-called blooming phenomenon that excess charges generated stretch over the peripheral regions. To suppress this blooming phenomenon, a vertical overflow drain structure has been adopted heretofore.
FIG. 8 illustrates in section the vertical transfer section 22 and the photoelectric conversion section 21 having the vertical overflow drain structure. In detail, a FP ( flat p-type) well 53 is formed on an n-type semiconductor substrate 51, and the vertical transfer section 22 and the photoelectric conversion section 21 are formed within the FP well 53. The vertical transfer section 22 comprises an n-type semiconductor layer 54, a p-type semiconductor layer 55 for preventing injection of charges and inflow of charges of smear components from the n-type semiconductor substrate 51 into the vertical transfer section 22, a vertical transfer electrode 58, and a light-screening film 60 for light screening. The photoelectric conversion section 21, on the other hand, comprises an n-type semiconductor layer 56, and a p.sup.+ -type semiconductor layer 57 for pixel isolation. It is noted that reference numerals 50 and 59 each denote a SiO.sub.2 film, and that a Si.sub.3 N.sub.4 film(not shown) is provided between the SiO.sub.2 film 50 and the transfer electrode 58. The FP well 53 is set approximately to a concentration of dopants of 5.times.10.sup.14 cm.sup.-3 and a thickness of 3 .mu.m, perfectly depleted due to the low concentration of dopants. Accordingly, excess charges generated in the photoelectric conversion section 21 will overflow beyond the barrier of the depleted FP well 53 toward the n-type semiconductor substrate 51 (vertical overflow drain structure). Meanwhile, between the n-type semiconductor layer 54 of the vertical transfer section 22 and the n-type substrate 51 is provided the p-type semiconductor layer 55, which is thicker in dopant level than the FP well 53, for preventing inflow and outflow of charges. Further, although not shown in FIG. 8, the aforementioned horizontal transfer section and the floating diffusion layer are, in general, also formed on the p-type semiconductor layer 55 within the FP well 53.
FIG. 6 shows the planar layout of the charge detecting section 24 in the vicinity of a floating diffusion layer 31 in the vertical overflow drain structure. The floating diffusion layer 131 is connected to a metal wiring 33 at a contact 32, and the metal wiring 33 in turn is connected to a gate electrode of the first-stage source follower driver transistor T1 at a contact 34. Normally, the photoelectric conversion section (not shown in FIG. 6), the vertical transfer section (not shown in FIG. 6), the horizontal transfer section 23, an output gate 25, the floating diffusion layer 31, and the reset transistor TR are formed within the FP well 53 on the n-type semiconductor substrate 51 shown in FIG. 8. Meanwhile, as shown in FIG. 6, the first-stage source follower driver transistor T1 is formed within another deep p-type well more heavily doped and formed deeper than the FP well 53 (hereinafter, referred to as "DP well") for preventing charges from flowing into the source and drain regions from the n-type semiconductor substrate. As a result, the FP well and the DP well are adjoining to each other by the ends at a boundary 35.
FIG. 7 shows a section of the first-stage source follower driver transistor T1 (taken from a line S - D in FIG. 6). In the figure, a DP well 42 is formed on an n-type semiconductor substrate 41, the DP well 42 having a gate electrode 48, an n-type source 49a, and a drain 49b formed therein to make up the transistor T1. The source 49a and the drain 49b are formed in some self-alignment fashion with respect to the gate electrode 48. It is to be noted that a Si.sub.3 N.sub.4 film(not shown) is provided between the SiO.sub.2 film 50 and the gate electrode 48. Also, as disclosed in Japanese Patent Laid-Open Publication Hei 1-283870 (1989), a lightly doped region may be provided between the gate electrode 48 and the drain 49b to reduce the capacity between the gate electrode 48 and the drain 49b.
As one method for enhancing the sensitivity of the solid state imaging device, charge-to-voltage conversion efficiency of the charge detecting section 24 as shown in FIG. 5 may be elevated. If the amount of charges transferred to the floating diffusion layer (a cathode side portion of diode D1) is Q, total capacity relative to the floating diffusion layer is C, and gain of the source follower circuit is G, then the output voltage V can be represented as V=G.multidot.Q/C. Also, the total capacity C contains, as capacity components, a junction capacity C1 between the floating diffusion layer and the well having the floating diffusion layer provided therein, a capacity C2 between the floating diffusion layer and the gate of the reset transistor TR adjoining thereto, a capacity C3 between the floating diffusion layer and the output gate 25 adjoining thereto, a capacity C4 had by an interconnection between the floating diffusion layer and the gate of the first-stage source follower driver transistor T1 (including capacity between interconnections, capacity between interconnections and semiconductor substrate, and capacity between gate and channel of the first-stage source follower driver transistor), and a capacity C5 between gate and drain of the first-stage source follower driver transistor. Accordingly, the total capacity C can be represented as C=C1+C2+C3+C4+C5, so that these capacities may be reduced to enhance the charge-to-voltage conversion efficiency.
The above-described prior art structure would require such an arrangement that the floating diffusion layer 31 be separated sufficiently apart from the boundary 35 between FP and DP wells and besides that the first-stage source follower driver transistor T1 be separated sufficiently apart from the boundary 35 between FP and DP wells. More specifically, since the two kinds of wells would diffuse through heat treatment, after ion implantation, to stretch laterally, the DP well would affect the characteristics of the reset transistor TR, the horizontal transfer section 23, the output gate 25, and the floating diffusion layer 31, while the FP well would affect the characteristics of the first-stage source follower driver transistor T1. Due to this, the boundary 35 between the DP well and the FP well needs to be separated sufficiently apart from both the floating diffusion layer 31 and the first-stage source follower driver transistor T1. Of course, the boundary 35 needs to be separated also from the reset transistor TR, the horizontal transfer section 23, and the output gate 25, but these do not matter in terms of layout. In fact, as shown in FIG. 9, at the boundary 35 between the FP well and the DP well, a dopant profile varies laterally over a width of about 10 .mu.m. Therefore, in order to make the concentration of dopants constant within each of the FP well 53 and the DP well 42, and to thereby obtain stable characteristics, the distance between the floating diffusion layer 31 and the first-stage source follower driver transistor T1 as shown in FIG. 6 needs to be at least 10 .mu.m or so. As a result of this, in the conventional structure, the interconnection 33 that connects the floating diffusion layer 31 and the gate of the first-stage source follower driver transistor T1 would be lengthened, so that an interconnection capacity C4 (more precisely, a capacity between interconnections and a capacity between the interconnection and semiconductor substrate, out of the C4) would result in a large one. For this reason, the charge-to-voltage conversion efficiency of the charge detecting section 24 would lower, causing its sensitivity to also lower, disadvantageously.
Also, there has been another problem that the capacity C5 between gate and drain of the first-stage source follower driver transistor T1 is too large.
Further, due to conduction by punch-through between source and drain of the first-stage source follower driver transistor T1, gate length of the transistor could not be shortened, so that the capacity between gate and channel of the first-stage source follower driver transistor T1 out of the interconnection capacity C4 could not be reduced, as a further problem.
Furthermore, due to concentration of electric fields in the vicinity of the drain of the first-stage source follower driver transistor T1, there would be generated electron and hole pairs by the impact ionization phenomenon, which would cause great noise.